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| v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es * 320 MHz Internal Performance * 3.7 ns Clock-to-Out (Pin-to-Pin) * 0.1 ns Input Set-Up * 0.25 ns Clock Skew Sp e ci f ic at ion s * 66 MHz PCI * CPLD and FPGA Integration * Single Chip Solution * 100% Resource Utilization with 100% Pin Locking * 3.3V Operation with 5.0V Input Tolerance * Very Low Power Consumption * Deterministic, User-Controllable Timing * Unique In-System Diagnostic and Debug capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft * 12,000 to 48,000 System Gates * Up to 249 User-Programmable I/O Pins * Up to 1080 Flip-Flops * 0.35 CMOS S X P r od u c t P ro fi l e A54SX08 Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Register Cells (Dedicated Flip-Flops) Maximum User I/Os Clocks JTAG PCI Clock-to-Out Input Set-Up (External) Speed Grades Temperature Grades Packages (by pin count) PLCC PQFP VQFP TQFP PBGA FBGA 8,000 12,000 768 512 256 130 3 Yes -- 3.7 ns 0.8 ns Std, -1, -2, -3 C, I, M 84 208 100 144, 176 -- 144 A54SX16 16,000 24,000 1,452 924 528 175 3 Yes -- 3.9 ns 0.5 ns Std, -1, -2, -3 C, I, M -- 208 100 176 -- -- A54SX16P 16,000 24,000 1,452 924 528 175 3 Yes Yes 4.4 ns 0.5 ns Std, -1, -2, -3 C, I, M -- 208 100 144, 176 -- -- A54SX32 32,000 48,000 2,880 1800 1,080 249 3 Yes -- 4.6 ns 0.1 ns Std, -1, -2, -3 C, I, M -- 208 -- 144, 176 313, 329 -- June 2003 1 (c) 2003 Actel Corporation 54SX Family FPGAs G e n e ra l D e s cr i p t i o n Actel's SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications. Actel's SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules"), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state O r d er i n g In f or m a t i o n A54SX16 P - 2 PQ 208 machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort. Further complementing SX's flexible routing structure is a hard-wired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX devices have easy-to-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time. Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) PP = Pre-production Package Lead Count Package Type BG = Ball Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack FG = Fine Pitch Ball Grid Array (1.0 mm) Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard -2 = Approximately 25% Faster than Standard -3 = Approximately 35% Faster than Standard Blank = Not PCI Compliant P = PCI Compliant Part Number A54SX08 A54SX16 A54SX16P A54SX32 = = = = 12,000 System Gates 24,000 System Gates 24,000 System Gates 48,000 System Gates 2 v3.1 5 4 S X F a m i l y F PG A s P ro d u ct P l a n Speed Grade* Std A54SX08 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 144-Pin Thin Quad Flat Pack (TQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX16 Device 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX16P Device 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 144-Pin Thin Quad Flat Pack (TQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX32 Device 144-Pin Thin Quad Flat Pack (TQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 313-Pin Plastic Ball Grid Array (PBGA) 329-Pin Plastic Ball Grid Array (PBGA) P P P -- -- -- -- -- -- P P P -- -- -- -- -- -- -1 -2 -3 C Application I M* Contact your Actel sales representative for product availability. Applications:C = CommercialAvailability: = Available*Speed Grade:-1 I = Industrial P = Planned -2 M = Military -- = Not Planned -3 Only Std, -1, -2 Speed Grade * Only Std, -1 Speed Grade = Approx. 15% faster than Standard = Approx. 25% faster than Standard = Approx. 35% faster than Standard P l a s t i c D e v i c e R e s ou r c es User I/Os (including clock buffers) Device A54SX08 A54SX16 A54SX16P A54SX32 PLCC 84-Pin 69 -- -- -- VQFP 100-Pin 81 81 81 -- PQFP 208-Pin 130 175 175 174 TQFP 144-Pin 113 -- 113 113 TQFP 176-Pin 128 147 147 147 PBGA 313-Pin -- -- -- 249 PBGA 329-Pin -- -- -- 249 FBGA 144-Pin 111 -- -- -- Package Definitions (Consult your local Actel sales representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch (1.0 mm) Ball Grid Array v3.1 3 54SX Family FPGAs S X F a m i l y A r ch i t e c tu r e The SX family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. P r o g r a m m a b l e I n t e r c o nn e c t E l e m e n t antifuse interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. The SX family provides efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (Figure 1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable Routing Tracks Metal 3 Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Figure 1 * SX Family Interconnect Elements Lo g ic M o du le D es ig n The SX family architecture is described as a "sea-of-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel's SX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 2 on page 5). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX FPGA. The clock source for the R-cell can be chosen from either the hard-wired clock or the routed clock. 4 v3.1 5 4 S X F a m i l y F PG A s The C-cell implements a range of combinatorial functions up to 5-inputs (Figure 3). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. S0 Routed Data Input S1 PSETB Direct Connect Input D Q Y HCLK CLKA, CLKB, Internal Logic CKS CKP CLRB Figure 2 * R-Cell D0 D1 Y D2 D3 Sa Sb DB A0 B0 A1 B1 Figure 3 * C-Cell Chip Architecture Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 4 on page 6). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. The SX family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. M od u le O r g a niz a t io n Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while v3.1 5 54SX Family FPGAs R-Cell Routed Data Input S1 D0 D1 PSETB Direct Connect Input D2 D Q Y D3 C-Cell S0 Y Sa Sb HCLK CLKA, CLKB, Internal Logic CKS CKP CLRB DB A0 B0 A1 B1 Cluster 1 Cluster 2 Cluster 2 Cluster 1 Type 1 SuperCluster Figure 4 * Cluster Organization Ro ut in g Re so u r ce s Type 2 SuperCluster Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 5 and Figure 6 on page 7). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.4 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place and route software to minimize signal propagation delays. Actel's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hard wired from the HCLK buffer to the clock select MUX in each R-cell. This provides a fast propagation path for the clock signal, enabling the 3.7 ns clock-to-out (pin-to-pin) performance of the SX devices. The hard-wired clock is tuned to provide clock skew as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the SX device. 6 v3.1 5 4 S X F a m i l y F PG A s O t h er A r c h i te c t ur a l F e at u re s Technology Actel's SX family is implemented on a high-voltage twin-well CMOS process using 0.35 design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ("on" state) resistance of 25 with capacitance of 1.0 fF for low signal impedance. Direct Connect * No antifuses * 0.1 ns routing delay Fast Connect * One antifuse * 0.4 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Figure 5 * DirectConnect and FastConnect for Type 1 SuperClusters Direct Connect * No antifuses * 0.1 ns routing delay Fast Connect * One antifuse * 0.4 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 6 * DirectConnect and FastConnect for Type 2 SuperClusters v3.1 7 54SX Family FPGAs P e r f o r m an c e B o u nd a r y S c an T e st i ng ( B S T ) The combination of architectural features described above enables SX devices to operate with internal clock frequencies exceeding 300 MHz, enabling very fast execution of even complex logic functions. Thus, the SX family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an SX device with dramatic improvements in cost and time to market. Using timing-driven place and route tools, designers can achieve highly deterministic device performance. With SX devices, designers do not need to use complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macros in HDL code to achieve high performance. I/O Modules All SX devices are IEEE 1149.1 compliant. SX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins in conjunction with the program fuse. The functionality of each pin is described in Table 2.In the dedicated test mode, TCK, TDI and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10k. TMS can be pulled LOW to initiate the test sequence. The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. . Table 2 * Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) TCK, TDI, TDO are dedicated BST pins No need for pull-up resistor for TMS Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are flexible and may be used as I/Os Use a pull-up resistor of 10k on TMS Each I/O on an SX device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in SX FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. P o w er R e q u i r e m e nt s D e v el op m e n t T o o l S u p po r t The SX family supports 3.3V operation and is designed to tolerate 5.0V inputs. (Table 1). Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low-resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture on the market. Table 1 * Supply Voltages VCCA A54SX08 A54SX16 A54SX32 3.3V A54SX16-P Note: 3.3V 3.3V 3.3V 3.3V 5.0V 3.3V 5.0V 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 3.3V VCCI Maximum Maximum Input Output VCCR Tolerance Drive The SX devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place and route tools. Designer Advantage, Actel's suite of FPGA development point tools for PCs and Workstations, includes the ACTgen Macro Builder, Designer with DirectTime timing driven place and route and analysis tools, and device programming software. In addition, the SX devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. 5.0V 5.0V 3.3V 5.0V 5.0V A54SX16-P has three different entries because it is capable of both a 3.3V and a 5V drive. 8 v3.1 5 4 S X F a m i l y F PG A s S X P r o b e C i r cu it C o n t r o l P i n s recommended that the TRST pin be left floating. De s ig n Co ns id e r at io ns The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 7 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. The TRST pin is equipped with a pull-up resistor. To remove the boundary scan state machine from the reset state during probing, it is Channel The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the Probe Circuitry. 16 SX FPGA TDI TCK TMS Serial Connection Silicon Explorer II TDO PRA PRB Figure 7 * Probe Setup v3.1 9 54SX Family FPGAs 3 . 3V / 5V O p e ra t i n g C o n di t i o n s A b s o l u t e Ma x i m u m R a ti n g s 1 Symbol VCCR2 VCCA2 VCCI2 VCCI2 VI VO IIO TSTG Parameter DC Supply Voltage3 DC Supply Voltage DC Supply Voltage (A54SX08, A54SX16, A54SX32) DC Supply Voltage (A54SX16P) Input Voltage Output Voltage I/O Source Sink Current3 Storage Temperature Limits -0.3 to +6.0 -0.3 to +4.0 -0.3 to +4.0 Units V V V Parameter Temperature Range1 3.3V Power Supply Tolerance 5.0V Power Supply Tolerance R e c o m m e n de d O p e r at i n g C o n di ti o n s Commer cial 0 to+70 10 Industrial -40 to +85 10 Military -55 to +125 10 Units C %VC C -0.3 to +6.0 -0.5 to +5.5 -0.5 to +3.6 -30 to +5.0 -65 to +150 V V V mA C 5 10 10 %VC C Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. VCCR in the A54SX16P must be greater than or equal to VCCI during power-up and power-down sequences and during normal operation. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND - 0.5V, the internal protection diodes will forward-bias and can draw excessive current. E l e ct r i c al S pe c i fi ca t i o n s Commercial Symbol Parameter (IOH = -20uA) (CMOS) VOH (IOH = -8mA) (TTL) (IOH = -6mA) (TTL) (IOL= 20uA) (CMOS) VOL VIL VIH tR , tF CIO ICC ICC(D) Input Transition Time tR, tF CIO I/O Capacitance Standby Current, ICC ICC(D) IDynamic VCC Supply Current 2.0 50 10 4.0 (IOL = 12mA) (TTL) (IOL = 8mA) (TTL) 0.8 2.0 50 10 4.0 0.10 0.50 0.50 0.8 V V ns pF mA V Min. (VCCI - 0.1) 2.4 Max. VCCI VCCI 2.4 VCCI Industrial Min. (VCCI - 0.1) Max. VCCI V Units See "Evaluating Power in 54SX Devices" on page 18 10 v3.1 5 4 S X F a m i l y F PG A s P C I C o m p l i a n ce f or t h e 54 S X F a m i l y The 54SX family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. A54SX16P DC Specifications (5.0V PCI Operation) Symbol VCCA VCCR VCCI VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL Parameter Supply Voltage for Array Supply Voltage required for Internal Biasing Supply Voltage for IOs Input High Input Low Voltage1 Voltage1 Condition Min. 3.0 4.75 4.75 2.0 -0.5 Max. 3.6 5.25 5.25 VCC + 0.5 0.8 70 -70 Units V V V V V A A V V pF pF pF Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage2 Input Pin Capacitance3 CLK Pin Capacitance IDSEL Pin Capacitance4 VIN = 2.7 VIN = 0.5 IOUT = -2 mA IOUT = 3 mA, 6 mA 5 2.4 0.55 10 12 8 Notes: 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. v3.1 11 54SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Symbol Parameter Condition 0 < VOUT 1.41 1.4 VOUT < 2.41, 2 3.1 < VOUT < VCC1, 3 Min. -44 -44 + (VOUT - 1.4)/0.024 Max. Units mA mA IOH(AC) Switching Current High Equation A: on page 13 -142 95 VOUT/0.023 Equation B: on page 13 206 -25 + (VIN + 1)/0.015 1 1 5 5 mA mA mA V/ns V/ns mA mA (Test Point) VOUT = 3.13 VOUT 2.21 2.2 > VOUT > 0.551 0.71 > VOUT > 01, 3 IOL(AC) Switching Current High (Test Point) ICL slewR slewF Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.713 -5 < VIN -1 0.4V to 2.4V 2.4V to 0.4V load4 load4 Notes: 1. Refer to the V/I curves in Figure 8. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 8. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin output buffer 10 pF 1k 1k 1/2 in. max. VCC 12 v3.1 5 4 S X F a m i l y F PG A s Figure 8 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family. 0.50 0.45 0.40 0.35 0.30 Current (A) 0.25 0.20 0.15 0.10 0.05 0 1 -0.05 -0.10 -0.15 -0.20 Voltage Out PCI IOH Mininum SX PCI IOH PCI IOH Maximum 2 3 4 5 6 PCI IOL Mininum SX PCI IOL PCI IOL Maximum Figure 8 * 5.0V PCI Curve for A54SX16P Family Equation A: IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V v3.1 13 54SX Family FPGAs A 5 4 S X 1 6 P D C S p e c i f i ca t i on s ( 3 . 3 V P C I O p e r a t i on ) Symbol VCCA VCCR VCCI VIH VIL IIPU IIL VOH VOL CIN CCLK CIDSEL Parameter Supply Voltage for Array Supply Voltage required for Internal Biasing Supply Voltage for IOs Input High Voltage Input Low Voltage Input Pull-up Voltage1 Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance3 CLK Pin Capacitance IDSEL Pin Capacitance4 2 Condition Min. 3.0 3.0 3.0 0.5VCC -0.5 0.7VCC Max. 3.6 3.6 3.6 VCC + 0.5 0.3VCC 10 Units V V V V V V A V V pF pF pF 0 < VIN < VCC IOUT = -500 A IOUT = 1500 A 5 0.9VCC 0.1VCC 10 12 8 Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 3. Absolute maximum pin capacitance for a PCI input is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 14 v3.1 5 4 S X F a m i l y F PG A s A 54SX16P AC Specifications (3.3V PCI Operation) Symbol Parameter Condition 0 < VOUT 0.3VCC1 0.3VCC VOUT < 0.9VCC1 0.7VCC < VOUT < VCC1, 2 Min. Max. Units mA Switching Current High IOH(AC) (Test Point) Switching Current High IOL(AC) (Test Point) ICL ICH slewR slewF Low Clamp Current High Clamp Current Output Rise Slew Output Fall Slew Rate3 Rate3 -12VCC -17.1 + (VCC - VOUT) Equation C: on page 16 -32VCC mA VOUT = 0.7VCC2 VCC > VOUT 0.6VCC1 0.6VCC > VOUT > VOUT = 0.18VCC -3 < VIN -1 -3 < VIN -1 0.2VCC to 0.6VCC load 0.6VCC to 0.2VCC load 2 mA mA mA 0.18VCC > VOUT > 0 0.1VCC1 1, 2 16VCC 26.7VOUT -25 + (VIN + 1)/0.015 25 + (VIN - VOUT - 1)/0.015 1 1 4 4 on page 16 mA mA mA V/ns V/ns 38VCC Notes: 1. Refer to the V/I curves in Figure 9. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. "Switching Current High" specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 9. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin output buffer 10 pF 1k 1k 1/2 in. max. VCC v3.1 15 54SX Family FPGAs Figure 9 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family. 0.50 0.45 0.40 0.35 0.30 Current (A) PCI IOL Maximum 0.25 0.20 SX PCI IOL 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 Voltage Out 1 PCI IOH Minimum 2 3 4 PCI IOH Maximum PCI IOL Minimum SX PCI IOH 5 6 Figure 9 * 3.3V PCI Curve for A54SX16P Family Equation C: IOH = (98.0/VCC) * (VOUT - VCC) * (VOUT + 0.4VCC) for VCC > VOUT > 0.7 VCC Equation D: IOL = (256/VCC) * VOUT * (VCC - VOUT) for 0V < VOUT < 0.18 VCC 16 v3.1 5 4 S X F a m i l y F PG A s P o we r - U p S e q u en c i n g VCCA VCCR VCCI Power-Up Sequence Comments A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V First 5.0V Second A54SX16P 3.3V 3.3V 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V First 5.0V Second 5.0V First 3.3V Second 3.3V First 5.0V Second No possible damage to device. No possible damage to device. Possible damage to device. No possible damage to device. No possible damage to device. No possible damage to device. Possible damage to device. 3.3V 5.0V 3.3V 3.3V 5.0V 3.3V 3.3V 5.0V 5.0V P o we r - D o w n S e qu e n ci ng VCCA VCCR VCCI Power-Down Sequence Comments A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V First 5.0V Second A54SX16P 3.3V 3.3V 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V First 5.0V Second 5.0V First 3.3V Second 3.3V First 5.0V Second No possible damage to device. Possible damage to device. No possible damage to device. No possible damage to device. No possible damage to device. No possible damage to device. Possible damage to device. 3.3V 5.0V 3.3V 3.3V 5.0V 3.3V 3.3V 5.0V 5.0V v3.1 17 54SX Family FPGAs E v a l u a ti n g P o w er i n 5 4 S X D e v i c es dissipation is defined as follows: PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net + (3) POutput Buffer + PInput Buffer 2 PAC = VCCA * [(m * CEQM * fm)Module + (n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output Buffer+ (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB + (4) (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK] D e f i n i t i o n o f T e r m s U s e d i n F o r m u la A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system's ability to dissipate heat. You should complete a power evaluation early in the design process to help identify potential heat-related problems in the system and to prevent the system from exceeding the device's maximum allowed junction temperature. The actual power dissipated by most applications is significantly lower than the power the package can dissipate. However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps: * Estimate the power consumption of the application. * Calculate the maximum power allowed for the device and package. * Compare the estimated power and maximum power values. E s t i m a t i ng P o w e r C o ns u m p ti o n m n p q1 q2 x y r1 r2 = = = = = = = = = = = = = = = = = = = = = = = The total power dissipation for the 54SX family is the sum of the DC power dissipation and the AC power dissipation. Use Equation 1 to calculate the estimated power consumption of your application. PTotal = PDC + PAC DC Power Dissipation s1 CEQM CEQI CEQO CEQCR CEQHV CEQHF CL fm fn fp fq1 fq2 fs1 (1) The power due to standby current is typically a small component of the overall power. The Standby power is shown below for commercial, worst case conditions (70C). Table 3 * ICC 4mA VCC 3.6V Power 14.4mW The DC power dissipation is defined in Equation 2 as follows: PDC = (Istandby)*VCCA + (Istandby)*VCCR + (Istandby)*VCCI + x*VOL*IOL + y*(VCCI - VOH)*VOH AC Power Dissipation Number of logic modules switching at fm Number of input buffers switching at fn Number of output buffers switching at fp Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock Number of I/Os at logic low Number of I/Os at logic high Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock Number of clock loads on the dedicated array clock Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffers in pF Equivalent capacitance of routed array clock in pF Variable capacitance of dedicated array clock Fixed capacitance of dedicated array clock Output lead capacitance in pF Average logic module switching rate in MHz Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Average dedicated array clock rate in MHz A54SX16 4.0 3.4 4.7 1.6 0.615 96 138 138 A54SX16P A54SX32 4.0 4.0 3.4 3.4 4.7 4.7 1.6 1.6 0.615 0.615 96 140 138 171 138 171 (2) The power dissipation of the 54SX Family is usually dominated by the dynamic power dissipation. Dynamic power dissipation is a function of frequency, equivalent capacitance and power supply voltage. The AC power A54SX08 CEQM (pF) 4.0 CEQI (pF) 3.4 CEQO (pF) 4.7 CEQCR (pF) 1.6 0.615 CEQHV CEQHF 60 87 r1 (pF) 87 r2 (pF) 18 v3.1 5 4 S X F a m i l y F PG A s G u i d e l i n e s f or C a l c u l a t i ng P ow e r C o n s u m p t i on A C P ow e r D i s s i pa t i o n The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follow: 20% of modules # inputs/4 # output/4 20% of register cells Second Routed Array Clock Loads (q2) = 20% of register cells = 35 pF Load Capacitance (CL) Average Logic Module Switching Rate = f/10 (fm) Average Input Switching Rate (fn) = f/5 Average Output Switching Rate (fp) = f/10 Average First Routed Array Clock Rate = f/2 (fq1) Average Second Routed Array Clock = f/2 Rate (fq2) Average Dedicated Array Clock Rate = f (fs1) Dedicated Clock Array clock loads (s1) = 20% of regular modules Sample Power Calculation Logic Modules (m) Inputs Switching (n) Outputs Switching (p) First Routed Array Clock Loads (q1) = = = = PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net + (6) POutput Buffer + PInput Buffer 2 PAC = VCCA * [(m * CEQM * fm)Module + (n * CEQI * fn)Input Buffer+ (p * (CEQO + CL) * fp)Output Buffer+ (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))RCLKB + (7) (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK] Step #1: Define Terms Used in Formula One of the designs used to characterize the A54SX family was a 528 bit serial in serial out shift register. The design utilized 100% of the dedicated flip-flops of an A54SX16P device. A pattern of 0101... was clocked into the device at frequencies ranging from 1 MHz to 200 MHz. Shifting in a series of 0101... caused 50% of the flip-flops to toggle from low to high at every clock cycle. Follow the steps below to estimate power consumption. The values provided for the sample calculation below are for the shift register design above. This method for estimating power consumption is conservative and the actual power consumption of your design may be less than the estimated power consumption. The total power dissipation for the 54SX family is the sum of the AC power dissipation and the DC power dissipation. PTotal = PAC (dynamic power) + PDC (static power) (5) 3.3 VCCA Module m Number of logic modules switching at fm (Used 50%) Average logic modules switching rate fm fm (MHz) (Guidelines: f/10) Module capacitance CEQM (pF) CEQM Input Buffer n Number of input buffers switching at fn fn Average input switching rate fn (MHz) (Guidelines: f/5) Input buffer capacitance CEQI (pF) CEQI Output Buffer p Number of output buffers switching at fp fp Average output buffers switching rate fp(MHz) (Guidelines: f/10) Output buffers buffer Capacitance CEQO (pF) CEQO Output Load capacitance CL (pF) CL RCLKA q1 Number of Clock loads q1 Capacitance of routed array clock (pF) CEQCR Average clock rate (MHz) fq1 Fixed capacitance (pF) r1 RCLKB Number of Clock loads q2 q2 Capacitance of routed array clock (pF) CEQCR Average clock rate (MHz) fq2 Fixed capacitance (pF) r2 HCLK Number of Clock loads s1 Variable capacitance of dedicated CEQHV array clock (pF) Fixed capacitance of dedicated CEQHF array clock (pF) Average clock rate (MHz) fs1 264 20 4.0 1 40 3.4 1 20 4.7 35 528 1.6 200 138 0 1.6 0 138 0 0.615 96 0 v3.1 19 54SX Family FPGAs Step #2: Calculate Dynamic Power Consumption PDC = (Istandby)*VCCA 10.89 0.02112 0.000136 0.000794 0.11208 0 0 PDC = .55mA*3.3V PDC = 0.001815W Step #4: Calculate Total Power Consumption VCCA*VCCA m*fm*CEQM n*fn*CEQI p*fp*(CEQO+CL) 0.5*(q1*CEQCR*fq1)+(r1*fq1) 0.5*(q2*CEQCR*fq2)+(r2*fq2) 0.5 *(s1 * CEQHV * fs1)+(CEQHF*fs1) PAC = 1.461W Step #3: Calculate DC Power Dissipation PTotal = PAC + PDC PTotal = 1.461 + 0.001815 PTotal = 1.4628W Step #5: Compare Estimated Power Consumption against Characterized Power Consumption DC Power Dissipation PDC = (Istandby)*VCCA + (Istandby)*VCCR + (Istandby)*VCCI + X*VOL*IOL + Y*(VCCI - VOH)*VOH (8) For a rough estimate of DC Power Dissipation, only use PDC = (Istandby)*VCCA. The rest of the formula provides a very small number that can be considered negligible. 1200 The estimated total power consumption for this design is 1.46W. The characterized power consumption for this design at 200 MHz is 1.0164W. Figure 10 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1000 Power Dissipation mW 800 600 400 200 0 0 20 40 60 80 100 120 140 160 180 200 Frequency MHz Figure 10 * Power Dissipation 20 v3.1 5 4 S X F a m i l y F PG A s J un c t i on T e m p e ra t u re ( T J ) The temperature that you select in Designer Series software is the junction temperature, not ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Use the equation below to calculate junction temperature. Junction Temperature = T + Ta Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P P = Power calculated from Estimating Power Consumption section ja = Junction to ambient of package. ja numbers are located in Package Thermal Characteristics section. P a ck a g e T he r m a l C h a r ac t e ri s ti cs The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. The maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follows: 150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 2.86W 28C/W ja (C/W) ja Still Air 32 32 28 38 30 20 20 23 18 38.8 ja 300 ft/min 22 24 21 32 23 17 14.5 17 13.5 26.7 Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic Quad Flat Pack (PQFP) with Heat Spreader Plastic Ball Grid Array (PBGA) Plastic Ball Grid Array (PBGA) Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Note: SX08 does not have a heat spreader. Pin Count 84 144 176 100 208 208 272 313 329 144 jc 12 11 11 10 8 3.8 3 3 3 3.8 Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W v3.1 21 54SX Family FPGAs 5 4S X T i m i n g M o de l * Input Delays I/O Module tINY = 1.5 ns Internal Delays Combinatorial Cell tIRD2 = 0.6 ns Predicted Routing Delays Output Delays I/O Module tDHL = 1.6 ns tPD =0.6 ns tRD1 = 0.3 ns tRD4 = 1.0 ns tRD8 = 1.9 ns I/O Module tDHL = 1.6 ns Register Cell D Q Register Cell D Q tRD1 = 0.3 ns tRD1 = 0.3 ns tENZH = 2.3 ns tSUD = 0.5 ns tHD = 0.0 ns Routed Clock tRCO = 0.8 ns tRCKH = 1.5 ns (100% Load) FMAX = 250 MHz Hard-Wired Clock tRCO = 0.8 ns tHCKH = 1.0 ns FHMAX = 320 MHz *Values shown for A54SX08-3, worst-case commercial conditions. H a r d- Wi r e d C lo c k R o u t ed C lo ck External Set-Up = tINY + tIRD1 + tSUD - tHCKH = 1.5 + 0.3 + 0.5 - 1.0 = 1.3 ns External Set-Up = tINY + tIRD1 + tSUD - tRCKH = 1.5 + 0.3 + 0.5 - 1.5 = 0.8 ns Clock-to-Out (Pin-to-Pin) = tRCKH + tRCO + tRD1 + tDHL = 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns Clock-to-Out (Pin-to-Pin) = tHCKH + tRCO + tRD1 + tDHL = 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns 22 v3.1 5 4 S X F a m i l y F PG A s Output Buffer Delays E D TRIBUFF PAD To AC test loads (shown below) VCC In Out VOL tDLH 50% 50% VOH 1.5V tDHL GND 1.5V En Out VCC 50% VCC 50% 1.5V VOL tENZL tENLZ GND 10% En Out GND VCC 50% 50% VOH 1.5V tENZH tENHZ GND 90% AC Test Loads Load 1 (Used to measure propagation delay) To the output under test 35 pF To the output under test Load 2 (Used to measure enable delays) VCC GND Load 3 (Used to measure disable delays) VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k 35 pF To the output under test R to VCC for tPLZ R to GND for tPHZ R = 1 k 5 pF In p u t B uf fe r D e l a y s C - C el l D e l a y s S A B VCC PAD INBUF Y Y 3V In Out GND tINY 1.5V 1.5V VCC 50% tINY 0V 50% S, A or B Out GND Out 50% 50% VCC 50% tPD 50% tPD tPD GND 50% VCC GND tPD 50% v3.1 23 54SX Family FPGAs R e g i s t e r C el l T i m i n g C h a ra c t er i s ti c s Fl ip -F lo ps D CLK PRESET CLR Q (Positive edge triggered) tHD D tSUD CLK tHPWH, tRPWH tHPWL, tRPWL tHP tRCO Q tCLR CLR tWASYN PRESET tPRESET T i m i n g C h a ra c t er i s ti c s L on g T r a c ks Timing characteristics for 54SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all 54SX family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout delays. C r i t ic al N e t s a nd T yp ic a l N e t s Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO=24) routing delays in the data sheet specifications section. Timing Derating Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. 54SX devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. T em p er a tu r e an d V o l t a ge D er a ti ng F a c to r s (Normalized to Worst-Case Commercial, T J = 70C, V CCA = 3.0V) Junction Temperature (TJ) VCCA 3.0 3.3 3.6 -55 0.75 0.70 0.66 -40 0.78 0.73 0.69 0 0.87 0.82 0.77 25 0.89 0.83 0.78 70 1.00 0.93 0.87 85 1.04 0.97 0.92 125 1.16 1.08 1.02 24 v3.1 5 4 S X F a m i l y F PG A s A 5 4 S X 0 8 Ti m i n g C h ar a c te r i s t i c s (Worst-Case Commercial Conditions, V CCR = 4.75V, V CCA, V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 2 0.6 0.7 0.8 0.9 ns Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.3 0.3 0.6 0.8 1.0 1.9 2.8 0.1 0.4 0.4 0.7 0.9 1.2 2.2 3.2 0.1 0.4 0.4 0.8 1.0 1.4 2.5 3.7 0.1 0.5 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns ns ns R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width 0.5 0.0 1.4 0.8 0.5 0.7 0.5 0.0 1.6 1.1 0.6 0.8 0.7 0.0 1.8 1.2 0.7 0.9 0.8 0.0 2.1 1.4 0.8 1.0 ns ns ns ns ns ns Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 2 1.5 1.5 1.7 1.7 1.9 1.9 2.2 2.2 ns ns Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.3 0.6 0.8 1.0 1.9 2.8 0.4 0.7 0.9 1.2 2.2 3.2 0.4 0.8 1.0 1.4 2.5 3.7 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v3.1 25 54SX Family FPGAs A 5 4 S X 0 8 T i m i n g C h ar a c te r i s t i c s (continued) (Worst-Case Commercial Conditions) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.7 350 1.4 1.4 0.1 3.1 320 1.0 1.0 1.6 1.6 0.2 3.6 280 1.1 1.2 1.8 1.8 0.2 4.2 240 1.3 1.4 2.1 2.1 0.2 1.5 1.6 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.1 2.1 0.1 0.3 0.3 1.3 1.4 1.4 1.5 1.5 1.5 2.4 2.4 0.2 0.3 0.3 1.5 1.6 1.7 1.7 1.7 1.8 2.7 2.7 0.2 0.4 0.4 1.7 1.8 1.9 2.0 1.9 2.0 3.2 3.2 0.2 0.4 0.4 2.0 2.1 2.2 2.3 2.2 2.3 ns ns ns ns ns ns ns ns ns ns ns TTL Output Module Timing1 tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 1.6 1.6 2.1 2.3 1.4 1.3 1.9 1.9 2.4 2.7 1.7 1.5 2.1 2.1 2.8 3.1 1.9 1.7 2.5 2.5 3.2 3.6 2.2 2.0 ns ns ns ns ns ns Note: 1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 26 v3.1 5 4 S X F a m i l y F PG A s A 5 4 S X 1 6 Ti m i n g C h ar a c te r i s t i c s (Worst-Case Commercial Conditions, V CCR = 4.75V, V CCA, V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 2 0.6 0.7 0.8 0.9 ns Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.3 0.3 0.6 0.8 1.0 1.9 2.8 0.1 0.4 0.4 0.7 0.9 1.2 2.2 3.2 0.1 0.4 0.4 0.8 1.0 1.4 2.5 3.7 0.1 0.5 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns ns ns R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width 0.5 0.0 1.4 0.8 0.5 0.7 0.5 0.0 1.6 1.1 0.6 0.8 0.7 0.0 1.8 1.2 0.7 0.9 0.8 0.0 2.1 1.4 0.8 1.0 ns ns ns ns ns ns Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 2 1.5 1.5 1.7 1.7 1.9 1.9 2.2 2.2 ns ns Predicted Input Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.3 0.6 0.8 1.0 1.9 2.8 0.4 0.7 0.9 1.2 2.2 3.2 0.4 0.8 1.0 1.4 2.5 3.7 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v3.1 27 54SX Family FPGAs A 5 4 S X 1 6 T i m i n g C h ar a c te r i s t i c s (continued) (Worst-Case Commercial Conditions) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.7 350 1.4 1.4 0.2 3.1 320 1.2 1.2 1.6 1.6 0.2 3.6 280 1.4 1.4 1.8 1.8 0.3 4.2 240 1.5 1.6 2.1 2.1 0.3 1.8 1.9 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.1 2.1 0.5 0.5 0.5 1.6 1.8 1.8 2.0 1.8 2.0 2.4 2.4 0.5 0.6 0.6 1.8 2.0 2.1 2.2 2.1 2.2 2.7 2.7 0.5 0.7 0.7 2.1 2.3 2.5 2.5 2.4 2.5 3.2 3.2 0.7 0.8 0.8 2.5 2.7 2.8 3.0 2.8 3.0 ns ns ns ns ns ns ns ns ns ns ns TTL Output ModuleTiming1 tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 1.6 1.6 2.1 2.3 1.4 1.3 1.9 1.9 2.4 2.7 1.7 1.5 2.1 2.1 2.8 3.1 1.9 1.7 2.5 2.5 3.2 3.6 2.2 2.0 ns ns ns ns ns ns Note: 1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 28 v3.1 5 4 S X F a m i l y F PG A s A 5 4 S X 1 6P T i m i n g C h ar a c te r i s t i c s (Worst-Case Commercial Conditions, V CCR = 4.75V, V CCA, V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 2 0.6 0.7 0.8 0.9 ns Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.3 0.3 0.6 0.8 1.0 1.9 2.8 0.1 0.4 0.4 0.7 0.9 1.2 2.2 3.2 0.1 0.4 0.4 0.8 1.0 1.4 2.5 3.7 0.1 0.5 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns ns ns R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width 0.5 0.0 1.4 0.9 0.5 0.7 0.5 0.0 1.6 1.1 0.6 0.8 0.7 0.0 1.8 1.3 0.7 0.9 0.8 0.0 2.1 1.4 0.8 1.0 ns ns ns ns ns ns Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 2 1.5 1.5 1.7 1.7 1.9 1.9 2.2 2.2 ns ns Predicted Input Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.3 0.6 0.8 1.0 1.9 2.8 0.4 0.7 0.9 1.2 2.2 3.2 0.4 0.8 1.0 1.4 2.5 3.7 0.5 0.9 1.2 1.6 2.9 4.3 ns ns ns ns ns ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v3.1 29 54SX Family FPGAs A 5 4 S X 1 6P T i m i n g C h ar a c te r i s t i c s (continued) (Worst-Case Commercial Conditions, V CCR = 4.75V, V CCA, V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.7 350 1.4 1.4 0.2 3.1 320 1.2 1.2 1.6 1.6 0.2 3.6 280 1.4 1.4 1.8 1.8 0.3 4.2 240 1.5 1.6 2.1 2.1 0.3 1.8 1.9 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tDLH tDHL tENZL tENZH tENLZ tENHZ tDLH tDHL tENZL tENZH tENLZ tENHZ Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.1 2.1 0.5 0.5 0.5 1.6 1.8 1.8 2.0 1.8 2.0 2.4 2.4 0.5 0.6 0.6 1.8 2.0 2.1 2.2 2.1 2.2 2.7 2.7 0.5 0.7 0.7 2.1 2.3 2.5 2.5 2.4 2.5 3.2 3.2 0.7 0.8 0.8 2.5 2.7 2.8 3.0 2.8 3.0 ns ns ns ns ns ns ns ns ns ns ns TTL Output Module Timing Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 2.4 2.3 3.0 3.3 2.3 2.8 2.8 2.9 3.4 3.8 2.7 3.2 3.1 3.2 3.9 4.3 3.0 3.7 3.7 3.8 4.6 5.0 3.5 4.3 ns ns ns ns ns ns TTL/PCI Output Module Timing Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 1.5 1.9 2.3 1.5 2.7 2.9 1.7 2.2 2.6 1.7 3.1 3.3 2.0 2.4 3.0 1.9 3.5 3.7 2.3 2.9 3.5 2.3 4.1 4.4 ns ns ns ns ns ns 30 v3.1 5 4 S X F a m i l y F PG A s A 5 4 S X 1 6P T i m i n g C h ar a c te r i s t i c s (continued) (Worst-Case Commercial Conditions V CCR = 3.0V, V CCA , V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units PCI Output Module Timing1 tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 1.8 1.7 0.8 1.2 1.0 1.1 2.0 2.0 1.0 1.2 1.1 1.3 2.3 2.2 1.1 1.5 1.3 1.5 2.7 2.6 1.3 1.8 1.5 1.7 ns ns ns ns ns ns TTL Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 2.1 2.0 2.5 3.0 2.3 2.9 2.5 2.3 2.9 3.5 2.7 3.3 2.8 2.6 3.2 3.9 3.1 3.7 3.3 3.1 3.8 4.6 3.6 4.4 ns ns ns ns ns ns Note: 1. Delays based on 10 pF loading. v3.1 31 54SX Family FPGAs A 5 4 S X 3 2 T i m i n g C h ar a c te r i s t i c s (Worst-Case Commercial Conditions, V CCR = 4.75V, V CCA, V CCI = 3.0V, T J = 70C) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module 2 0.6 0.7 0.8 0.9 ns Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.3 0.3 0.7 1.0 1.4 2.7 4.0 0.1 0.4 0.4 0.8 1.2 1.6 3.1 4.7 0.1 0.4 0.4 0.9 1.4 1.8 3.5 5.3 0.1 0.5 0.5 1.0 1.6 2.1 4.1 6.2 ns ns ns ns ns ns ns ns R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width 0.5 0.0 1.4 0.8 0.5 0.7 0.6 0.0 1.6 1.1 0.6 0.8 0.7 0.0 1.8 1.3 0.7 0.9 0.8 0.0 2.1 1.4 0.8 1.0 ns ns ns ns ns ns Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Delays2 0.3 0.7 1.0 1.4 2.7 4.0 0.4 0.8 1.2 1.6 3.1 4.7 0.4 0.9 1.4 1.8 3.5 5.3 0.5 1.0 1.6 2.1 4.1 6.2 ns ns ns ns ns ns 1.5 1.5 1.7 1.7 1.9 1.9 2.2 2.2 ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 32 v3.1 5 4 S X F a m i l y F PG A s A 5 4 S X 3 2 Ti m i n g C h ar a c te r i s t i c s (continued) (Worst-Case Commercial Conditions) `-3' Speed Parameter Description Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 2.7 350 1.4 1.4 0.3 3.1 320 1.9 1.9 1.6 1.6 0.4 3.6 280 2.1 2.1 1.8 1.8 0.4 4.2 240 2.4 2.4 2.1 2.1 0.5 2.8 2.8 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.1 2.1 0.85 1.23 1.30 2.4 2.4 2.7 2.7 2.7 2.8 2.4 2.4 0.98 1.4 1.5 2.7 2.7 3.0 3.1 3.1 3.2 2.7 2.7 1.1 1.6 1.7 3.0 3.1 3.5 3.6 3.5 3.6 3.2 3.2 1.3 1.9 2.0 3.5 3.6 4.1 4.2 4.1 4.3 ns ns ns ns ns ns ns ns ns ns ns TTL Output Module Timing1 tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z 1.6 1.6 2.1 2.3 1.4 1.3 1.9 1.9 2.4 2.7 1.7 1.5 2.1 2.1 2.8 3.1 1.9 1.7 2.5 2.5 3.2 3.6 2.2 2.0 ns ns ns ns ns ns Note: 1. Delays based on 35pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5pF. v3.1 33 54SX Family FPGAs P i n D e s c r i p ti o n CLKA/B Clock A and B TCK Test Clock These pins are 3.3V/5.0V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (For A54SX72A, these clocks can be configured as bidirectional.) GND Ground Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 2 on page 8). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TDI Test Data Input LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock This pin is the 3.3V/5.0V PCI/TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 2 on page 8). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TDO Test Data Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3V PCI or 5.0V PCI specifications. Unused I/O pins are automatically tristated by the Designer Series software. NC No Connection Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 2 on page 8). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TMS Test Mode Select This pin is not connected to circuitry within the device. PRA, I/O Probe A The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB, I/O Probe B The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 2 on page 8). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. V CCI Supply Voltage Supply voltage for I/Os. See Table 1 on page 8. V CCA Supply Voltage Supply voltage for Array. See Table 1 on page 8. V CCR Supply Voltage The Probe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. Supply voltage for input tolerance (required for internal biasing) See Table 1 on page 8. 34 v3.1 5 4 S X F a m i l y F PG A s P a ck a g e Pi n A s s i g nm en t s 84 -P in P LC C ( T o p Vie w ) 1 84 84-Pin PLCC v3.1 35 54SX Family FPGAs 84 -P in P LC C P ac k ag e Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A54SX08 Function VCCR GND VCCA PRA, I/O I/O I/O VCCI I/O I/O I/O TCK, I/O TDI, I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 A54SX08 Function VCCR I/O HCLK I/O I/O I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB 36 v3.1 5 4 S X F a m i l y F PG A s P a ck a g e Pi n A s s i g nm en t s (continued) 20 8 -P in P Q F P ( T op V ie w ) 208 1 208-Pin PQFP v3.1 37 54SX Family FPGAs 20 8 -P in P Q F P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 A54SX08 Function GND TDI, I/O I/O NC I/O NC I/O I/O I/O I/O TMS VCCI I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O VCCR GND VCCA GND I/O I/O NC I/O I/O I/O NC I/O I/O I/O NC VCCI VCCA I/O I/O I/O I/O I/O I/O NC I/O NC I/O GND I/O A54SX16, A54SX16P Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCR GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O A54SX32 Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCR GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number 54 55 56 57 58 59 60 61 62 63 64 65* 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 A54SX08 Function I/O I/O I/O I/O I/O I/O VCCI NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O NC PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC VCCI I/O I/O I/O I/O TDO, I/O I/O GND NC A54SX16, A54SX16P Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O A54SX32 Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 * Please note that Pin 65 in the A54SX32--PQ208 is a no connect (NC). 38 v3.1 5 4 S X F a m i l y F PG A s 20 8 -P in P Q F P ( C on t in u ed ) Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function Pin Number 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A54SX08 Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O VCCI NC NC I/O NC I/O I/O TCK, I/O A54SX16, A54SX16P Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O A54SX32 Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O 107 NC I/O I/O 108 I/O I/O I/O 109 I/O I/O I/O 110 I/O I/O I/O 111 I/O I/O I/O 112 I/O I/O I/O 113 VCCA VCCA VCCA 114 VCCI VCCI VCCI 115 NC I/O I/O 116 I/O I/O I/O 117 I/O I/O I/O 118 NC I/O I/O 119 I/O I/O I/O 120 I/O I/O I/O 121 NC I/O I/O 122 I/O I/O I/O 123 I/O I/O I/O 124 NC I/O I/O 125 I/O I/O I/O 126 I/O I/O I/O 127 I/O I/O I/O 128 GND GND GND 129 VCCA VCCA VCCA 130 GND GND GND 131 VCCR VCCR VCCR 132 I/O I/O I/O 133 I/O I/O I/O 134 NC I/O I/O 135 I/O I/O I/O 136 I/O I/O I/O 137 NC I/O I/O 138 I/O I/O I/O 139 I/O I/O I/O 140 NC I/O I/O 141 I/O I/O I/O 142 NC I/O I/O 143 I/O I/O I/O 144 VCCA VCCA VCCA 145 GND GND GND 146 I/O I/O I/O 147 VCCI VCCI VCCI 148 I/O I/O I/O 149 I/O I/O I/O 150 I/O I/O I/O 151 I/O I/O I/O 152 I/O I/O I/O 153 I/O I/O I/O 154 NC I/O I/O 155 NC I/O I/O 156 GND GND GND 157 * Please note that Pin 65 in the A54SX32--PQ208 is a no connect (NC). v3.1 39 54SX Family FPGAs P ac k a g e Pi n A s s i g nm en t s (continued) 14 4 -P in T Q F P ( T op V ie w) 144 1 144-Pin TQFP 40 v3.1 5 4 S X F a m i l y F PG A s 144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A54SX08 Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCR VCCA I/O I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O A54SX16P Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCR VCCA I/O I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O A54SX32 Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCR VCCA I/O I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 A54SX08 Function I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI A54SX16P Function I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI A54SX32 Function I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI v3.1 41 54SX Family FPGAs 144-Pin TQFP (Continued) Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 A54SX08 Function GND I/O I/O I/O I/O I/O I/O I/O VCCA VCCR I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O A54SX16P Function GND I/O I/O I/O I/O I/O I/O I/O VCCA VCCR I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O A54SX32 Function GND I/O I/O I/O I/O I/O I/O I/O VCCA VCCR I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O Pin Number 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A54SX08 Function I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX16P Function I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX32 Function I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O 42 v3.1 5 4 S X F a m i l y F PG A s P a ck a g e Pi n A s s i g nm en t s (continued) 17 6 -P in T Q F P ( T op V ie w ) 176 1 176-Pin TQFP v3.1 43 54SX Family FPGAs 17 6 -P in T Q F P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 A54SX08 Function GND TDI, I/O NC I/O I/O I/O I/O I/O I/O TMS VCCI NC I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O NC I/O NC I/O GND A54SX16, A54SX16P Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A54SX32 Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A54SX08 Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC VCCI I/O I/O I/O I/O TDO, I/O I/O A54SX16, A54SX16P Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O A54SX32 Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O 44 v3.1 5 4 S X F a m i l y F PG A s 17 6 -P in T Q F P ( C on t in u ed ) Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 A54SX08 Function GND NC NC I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O NC I/O NC NC VCCA GND VCCI I/O I/O I/O I/O I/O I/O NC NC A54SX16, A54SX16P Function GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O A54SX32 Function GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 A54SX08 Function GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VCCI I/O NC NC NC I/O I/O TCK, I/O A54SX16, A54SX16P Function GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O A54SX32 Function GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O v3.1 45 54SX Family FPGAs P ac k a g e Pi n A s s i g nm en t s (continued) 10 0 -P in V Q F P ( T op V ie w) 100 1 100-Pin VQFP 46 v3.1 5 4 S X F a m i l y F PG A s 10 0 -VQ FP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A54SX08 Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND VCCR I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O A54SX16, A54SX16P Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA GND VCCR I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A54SX08 Function GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB VCCR VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O A54SX16 A54SX16P Function GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB VCCR VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O v3.1 47 54SX Family FPGAs P ac k a g e Pi n A s s i g nm en t s (continued) 313-Pin PBGA (Top View) 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 48 v3.1 5 4 S X F a m i l y F PG A s 3 1 3 -P in P B G A Pin Number A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 AA1 AA3 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AB2 AB4 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC1 AC3 AC5 AC7 AC9 AC11 AC13 A54SX32 Function GND NC I/O I/O I/O I/O VCCR I/O I/O I/O I/O NC GND I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O NC I/O NC NC I/O I/O I/O I/O I/O I/O VCCI NC I/O I/O I/O I/O I/O I/O I/O I/O VCCR Pin Number AC15 AC17 AC19 AC21 AC23 AC25 AD2 AD4 AD6 AD8 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AE1 AE3 AE5 AE7 AE9 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 C1 C3 A54SX32 Function I/O I/O I/O I/O I/O NC GND I/O VCCI I/O I/O PRB, I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O TDO, I/O GND TCK, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI, I/O I/O Pin Number C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 E1 E3 E5 E7 E9 E11 E13 E15 E17 E19 E21 E23 E25 F2 F4 F6 F8 F10 F12 F14 F16 F18 A54SX32 Function NC I/O I/O I/O VCCI I/O I/O VCCI I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O NC I/O Pin Number F20 F22 F24 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 H2 H4 H6 H8 H10 H12 H14 H16 H18 H20 H22 H24 J1 J3 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 J25 K2 K4 K6 K8 A54SX32 Function I/O I/O I/O I/O TMS I/O I/O VCCI I/O CLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O NC I/O VCCI I/O I/O I/O I/O NC I/O I/O CLKA I/O I/O I/O GND I/O I/O I/O I/O I/O VCCI v3.1 49 54SX Family FPGAs 31 3 -P in P B G A ( C o nt in ue d ) Pin Number K10 K12 K14 K16 K18 K20 K22 K24 L1 L3 L5 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 M2 M4 M6 M8 M10 M12 M14 M16 M18 M20 M22 M24 N1 A54SX32 Function I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND VCCI I/O I/O I/O I/O I/O Pin Number N3 N5 N7 N9 N11 N13 N15 N17 N19 N21 N23 N25 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 A54SX32 Function VCCA VCCR I/O VCCI GND GND GND I/O I/O I/O VCCR VCCA I/O I/O I/O I/O I/O GND GND I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O Pin Number R21 R23 R25 T2 T4 T6 T8 T10 T12 T14 T16 T18 T20 T22 T24 U1 U3 U5 U7 U9 U15 U17 U19 U21 U23 U25 V2 V4 V6 V8 V10 V12 V14 V16 A54SX32 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O NC Pin Number V18 V20 V22 V24 W1 W3 W5 W7 W9 W11 W13 W15 W17 W19 W21 W23 W25 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 A54SX32 Function I/O I/O VCCA VCCI I/O I/O I/O NC I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC 50 v3.1 5 4 S X F a m i l y F PG A s P a ck a g e Pi n A s s i g nm en t s (continued) 329-Pin PBGA (Top View) 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 v3.1 51 54SX Family FPGAs 3 2 9 -P in P B G A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 A54SX32 Function GND GND VCCI NC I/O I/O VCCI NC I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O I/O I/O NC VCCI GND VCCI I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O VCCI I/O Pin Number AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 A54SX32 Function VCCI I/O GND I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND VCCI NC I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC Pin Number AC22 AC23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 A54SX32 Function VCCI GND VCCI GND I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O GND VCCI NC TDI, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 A54SX32 Function VCCI GND NC I/O I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O VCCA VCCR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O 52 v3.1 5 4 S X F a m i l y F PG A s 3 2 9 -P in P B G A Pin Number G4 G20 G21 G22 G23 H1 H2 H3 H4 H20 H21 H22 H23 J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 K4 K10 K11 K12 K13 K14 K20 K21 K22 K23 L1 L2 L3 L4 L10 L11 L12 L13 L14 L20 L21 A54SX32 Function I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCR GND GND GND GND GND VCCR I/O Pin Number L22 L23 M1 M2 M3 M4 M10 M11 M12 M13 M14 M20 M21 M22 M23 N1 N2 N3 N4 N10 N11 N12 N13 N14 N20 N21 N22 N23 P1 P2 P3 P4 P10 P11 P12 P13 P14 P20 P21 P22 P23 R1 R2 R3 R4 A54SX32 Function I/O NC I/O I/O I/O VCCA GND GND GND GND GND VCCA I/O I/O VCCI I/O I/O I/O I/O GND GND GND GND GND NC I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O Pin Number R20 R21 R22 R23 T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 U23 V1 V2 V3 V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 A54SX32 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O GND I/O I/O I/O I/O I/O Pin Number Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 A54SX32 Function I/O I/O VCCA VCCR I/O I/O I/O I/O I/O I/O GND I/O I/O I/O v3.1 53 54SX Family FPGAs P ac k a g e Pi n A s s i g nm en t s (Continued) 144-Pin FBGA (Top View) 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 54 v3.1 5 4 S X F a m i l y F PG A s 14 4 -P in F B G A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A54SX08 Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 A54SX08 Function I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O VCCR I/O GND GND GND VCCI I/O GND I/O I/O I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O VCCR Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A54SX08 Function I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O v3.1 55 54SX Family FPGAs L i s t o f C ha n g es The following table lists critical changes that were made in the current version of the document. Previous version v3.0.1 Changes in current version (v3.1) 1 Page The storage temperature in the "Absolute Maximum Ratings " table on page 10 was page 10 updated. Table 1 on page 8 was updated. page 8 D a ta s he e t C a te g o ri es In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production." The definition of these categories are as follows: Product Brief The product brief is a modified version of an advanced datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. A d v an ce d This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates but not for production. U n ma r k ed ( pr o d uc t io n ) This datasheet version contains information that is considered to be final. 56 v3.1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 Actel Hong Kong 39th Floor One Pacific Place 88 Queensway Admiralty, Hong Kong Tel: 852-22735712 572137-4/6.03 |
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